From 4e6174c72b182b4e10556950cc4be63422df131a Mon Sep 17 00:00:00 2001 From: Marek Szuba Date: Fri, 13 Aug 2021 12:31:04 +0100 Subject: dev-db/postgresql: enable native spinlock support on riscv Don't bother with a revbump even though this is a run-time change - 13.4 and 14_beta3 were released yesterday so in the rather unlikely event of someone already running a PostgreSQL server on a Gentoo/RISC-V system, they will receive this change along with the the hopefully-imminent version bump. Signed-off-by: Marek Szuba --- .../files/postgresql-13.3-riscv-spinlocks.patch | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 dev-db/postgresql/files/postgresql-13.3-riscv-spinlocks.patch (limited to 'dev-db/postgresql/files') diff --git a/dev-db/postgresql/files/postgresql-13.3-riscv-spinlocks.patch b/dev-db/postgresql/files/postgresql-13.3-riscv-spinlocks.patch new file mode 100644 index 000000000000..86d1fae20d87 --- /dev/null +++ b/dev-db/postgresql/files/postgresql-13.3-riscv-spinlocks.patch @@ -0,0 +1,26 @@ +--- a/src/include/storage/s_lock.h ++++ b/src/include/storage/s_lock.h +@@ -315,12 +315,12 @@ + #endif /* __ia64__ || __ia64 */ + + /* +- * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available. ++ * On ARM, ARM64 and RISC-V, we use __sync_lock_test_and_set(int *, int) if available. + * + * We use the int-width variant of the builtin because it works on more chips + * than other widths. + */ +-#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) ++#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) || defined(__riscv) + #ifdef HAVE_GCC__SYNC_INT32_TAS + #define HAS_TEST_AND_SET + +@@ -337,7 +337,7 @@ + #define S_UNLOCK(lock) __sync_lock_release(lock) + + #endif /* HAVE_GCC__SYNC_INT32_TAS */ +-#endif /* __arm__ || __arm || __aarch64__ || __aarch64 */ ++#endif /* __arm__ || __arm || __aarch64__ || __aarch64 || __riscv */ + + + /* S/390 and S/390x Linux (32- and 64-bit zSeries) */ -- cgit v1.2.3